Voltage ramp generator
Summary: Using the MSP-EXP430FG4618 Development Tool and the MSP430FG4618 device implement a voltage ramp generator Basic Timer1.
Voltage ramp generator
Introduction
This laboratory gives an example of the use of the DAC available in the MSP-EXP430FG4618 Development Tool. The DAC module reference is obtained from the ADC module. The DAC is configured with 12 bits resolution in straight binary format. The DAC’s output value is updated every 1 msec by a Timer_A ISR. The buttons SW1 and SW2 are used to manually modify the DAC’s output.
Overview
This laboratory ( Lab1_DAC.c )implements a voltage ramp generator. The DAC module reference is obtained from the ADC module. The DAC is configured with 12-bit resolution, in straight binary format. The output of the DAC value is updated once every 1 msec by an interrupt service routine (ISR) generated by Timer_A. The push buttons SW1 and SW2 are used to manually modify the output of the DAC value. When the microcontroller is not performing any task, it enters low power mode.
Resources
The DAC12_0 module uses VREF+ as reference voltage. It is therefore necessary to activate this reference voltage in the ADC12 module.
The DAC12_0 is connected to Port P6.6 on the Header 8 pin 7. Connect the oscilloscope probe to this port pin.
The output of the DAC is updated whenever Timer_A generates an interrupt. This peripheral is configured to generate an interrupt with a 1 msec time period.
After refreshing the output of the DAC, the system returns to low power mode LPM3.
The push buttons SW1 and SW2 allow the output of the DAC value to be changed manually.
The resources used by the application are:
- Timer_A;
- DAC12;
- I/O ports;
- FLL+;
- Interrupts.
Software application organization
The application starts by stopping the Watchdog Timer.
Then, the ADC12’s reference voltage is activated and set to 2.5 V. A delay is used to allow the reference voltage to settle. During this time period, the device enters low power mode LPM0. The delay period, which is controlled by Timer_A, enables an interrupt when it completes. The interrupt wakes the device and proceeds with the execution of the application.
Timer_A is reconfigured to generate an interrupt once every 1 msec. This interrupt service routine (ISR) updates the output of the DAC.
Ports P1.0 and P1.1 are connected to buttons SW1 and SW2. The ports are configured as inputs with interrupt capability, such that the ISR can decode which button is pushed. If the interrupt source is due to button SW1, then the output of the DAC is increased. If the interrupt source is due to button SW2, then the output of the DAC is decreased.
System configuration
FLL+ configuration
FLL_CTL0 |= DCOPLUS | XCAP18PF; // DCO+ set,
// freq = xtal x D x N+1
SCFI0 |= FN_4; // x2 DCO freq, // 8MHz nominal DCO
SCFQCTL = 121; // (121+1) x 32768 x 2 = 7.99 MHz
Reference voltage selection
The DAC12_0 uses the signal VREF+ as reference voltage. What is the value to write to the configuration register in order to obtain the internally available reference?
ADC12CTL0 = REF2_5V | REFON; // Internal 2.5V ref onDAC12 configuration
The DAC12_0 is configured with 12-bit resolution. The output is updated immediately when a new DAC12 data value is written in straight binary data format to the DAC12_0DAT register.
The full-scale output must be equal to the VREF+ 2.5 V internal reference voltage. Choose a compromise solution between the settling time and current consumption, by selecting a medium frequency and current for both input and output buffers. Configure the following register in order to meet these specifications:
DAC12_0DAT = 0x00; // DAC_0 output 0V
DAC12_0CTL = DAC12IR | DAC12AMP_5 | DAC12ENC;
// DAC_0 -> P6.6,
// DAC_1 -> P6.7,
// DAC reference Vref,
// 12 bits resolution,
// Immediate load,
// DAC full scale output,
// Medium speed/current,
// Straight binary,
// Not grouped
Timer_A configuration
Configure Timer_A register to enable an interrupt once every 1 msec. Use the ACLK clock signal as the clock source. This timer is configured in count up mode in order to count until the TAR value reaches the TACCR0 value.
// Before entering in LPM0:
TACTL = TACLR | MC_1 | TASSEL_2; // up mode, SMCLK
// Timer_A ISR:
TAR = 0; // TAR reset
TACCR0 = 13600; // Delay to allow Ref to settle
TACCTL0 |= CCIE; // Compare-mode interrupt
TACTL = TACLR | MC_1 | TASSEL_2; // up mode, SMCLK
//*********************************************************
// ISR to TACCRO from Timer A
//*********************************************************
#pragma vector=TIMERA0_VECTOR
__interrupt void TimerA0_ISR (void)
{
DAC12_0DAT++; // Increase DAC's output
if (DAC12_0DAT == 0xfff)
DAC12_0DAT = 0; // reset DAC's output
if (flag == 1) // if flag active exite LPM0
{
flag = 0;
LPM0_EXIT;
}
} I/O Ports configuration
Port P1 uses the bits P1.0 and P1.2 to activate the ISR whenever the push buttons SW1 and SW2 are activated (low-to-high transition).
// SW1 and SW2 ports configuration
P1SEL &= ~0x03; // P1.0 and P1.1 I/O ports
P1DIR &= ~0x03; // P1.0 and P1.1 digital inputs
P1IFG = 0x00; // clear all interrupts pending
P1IE |= 0x03; // enable port interrupts
DAC12_0 is connected to P6.6. Configure P6 as a special function output:
// P6.6 (DAC12_0 output)
// There is no need to configure P6.6 as a
// special function output since it was configured in the
// DAC12 configuration register (DAC12_0CTL) using
// DAC12OPS = 0
//*********************************************************
// Port1 Interrupt Service Rotine
//*********************************************************
#pragma vector=PORT1_VECTOR
__interrupt void PORT1_ISR (void)
{
if (P1IFG & 0x01) // SW1 generate interrupt
DAC12_0DAT += 400; // DAC's output increases
if (P1IFG & 0x02) // SW2 generate interrupt
DAC12_0DAT -= 400; // DAC's output decreases
P1IFG = 0x00; // clean all pending interrupts
}
Analysis of operation
Observe the analogue signal using an oscilloscope
After compiling the project and starting the debug session, monitor the operation of the application using an oscilloscope probe connected to pin 7 of Header 8 (P6.6).
Measure the current drawn
Assign different values to the bits set in DAC12AMP0. Suspend the execution of the application then directly change the registers. Do not forget that this change requires suspending the operation of the DAC12 by disabling the bit DAC12ENC. Afterwards, this bit must be enabled.
Please note the special cases relating to:
- DAC12 off;
- High impedance output and DAC12 off;
- Output: 0 V.
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